The Terasic DE5-Net Stratix V GX FPGA Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 3/4-length form-factor package, the DE5-Net is designed for the most demanding high-end applications, empowered with the top-of-the-line Altera Stratix V GX, delivering the best system-level integration and flexibility in the industry.

The Stratix® V GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps, allowing the DE5-Net to be fully compliant with version 3.0 of the PCI Express standard, as well as allowing an ultra low-latency, straight connections to four external 10G SFP+ modules. Not relying on an external PHY will accelerate mainstream development of network applications enabling customers to deploy designs for a broad range of high-speed connectivity applications. For designs that demand high capacity and high speed for memory and storage, the DE5-Net delivers with two independent banks of DDR3 SO-DIMM RAM, four independent banks of Cypress QDRII+ SRAM or functional compatible SRAMS provided by GSI and ISSI, high-speed parallel flash memory, and four SATA ports. The feature-set of the DE5-Net fully supports all high-intensity applications such as low-latency trading, cloud computing, high-performance computing, data acquisition, network processing, and signal processing.

FPGA
FPGA
Altera Stratix V GX FPGA (5SGXEA7N2F45C2)
FPGA Configuration
On-Board USB Blaster II or JTAG header for FPGA programming
Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory
Memory
Memory
Two Independent DDR3 SODIMM Socket, Up to 8GB 800 MHz or 4GB 933 MHz for each socket
Four Independent 550MHz SRAM, 18-bits data bus and 72Mbit for each
256MB FLASH
Communication
Communication Ports
Four SFP+ connectors
PCI Express (PCIe) x8 edge connector (includes Windows PCIe drivers)
One RS422 expansion header
Others
General user input / output:
4 LEDs
1 LED Array
4 push-buttons
4 slide switches
2 seven-segment displays
SMA clock input / output
On-Board Clock
50MHz Oscillator
Programmable oscillators Si570, CDCM61001 and CDCM61004
System Monitor and Control
Temperature sensor
Fan control
Power
PCI Express 6-pin power connector, 12V DC Input
PCI Express edge connector power
Mechanical Specification
PCI Express standard height and 3/4-length

Block Diagram

主产品订购

No	产品名称	售价(RMB)
1.	[DE5-Net-550] DE5-Net Development Kit 产品编号: P0205  重量: 3,500g	￥56,250

选购配件 (如需选购, 请与主产品同时订购)

No	配件名称	售价(RMB)
1.	[SW-OPENCL] SW-OPENCL-SDK/DKE, license 产品编号: P0166  重量: 100g	￥2,000
2.	[OTB]OCXO Timing Board 产品编号: P0531  重量: 300g	￥2,295

Document

标题	版本	档案大小(KB)	新增日期	下载
DE5-Net User Manual	1.0.5	8894	2017-08-04

CD-ROM

BSP(Board Support Package) for Altera SDK OpenCL 16.1

标题	版本	档案大小(KB)	新增日期	下载
DE5-Net OpenCL BSP for Windows	1.1.0		2017-05-25
OpenCL User Manual	1.0.2	2272	2017-04-26
DE5-Net OpenCL BSP for Linux	1.0.2		2017-04-26

BSP(Board Support Package) for Altera SDK OpenCL 16.0

标题	版本	档案大小(KB)	新增日期	下载
DE5-Net OpenCL BSP for Windows			2016-12-20
OpenCL User Manual		2174	2016-11-01
DE5-Net OpenCL BSP for Linux			2016-11-01

BSP (Board Support Package) for Altera SDK OpenCL 14.0/14.1 - Network Platform

标题	版本	档案大小(KB)	新增日期	下载
DE5-Net Network BSP for Linux			2016-08-11
DE5-Net Network BSP for Windows			2016-08-11
User Manual for OpenCL - Network Platform		2703	2016-08-11

BSP(Board Support Package) for Altera SDK OpenCL 14.0/14.1

标题	版本	档案大小(KB)	新增日期	下载
DE5-Net OpenCL BSP for Windows			2015-05-05
OpenCL User Manual	1.0	2500	2014-11-11
DE5-Net OpenCL BSP for Linux			2014-11-11

BSP(Board Support Package) for Altera SDK OpenCL 13.1

标题	版本	档案大小(KB)	新增日期	下载
OpenCL User Manual		3009	2014-11-11
DE5-Net OpenCL BSP for Windows			2014-02-07
DE5-Net OpenCL BSP for Linux			2014-02-07