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【DE10-Lite】TERASIC友晶 DE10-Lite Board
- 产品型号: DE10-Lite
- 产品品牌: TERASIC友晶科技/Intel FPGA
- 产品规格: MAX 10 10M50DAF484C7G Device
- 产品价格: 欢迎咨询采购,量多优惠多,提供完善的售后保障和支持!
- 咨询热线:18062095810
Terasic DE10-Lite is a cost-effective Altera MAX 10 based FPGA board. The board utilizes the maximum capacity MAX 10 FPGA, which has around 50K logic elements(LEs) and on-die analog-to-digital converter (ADC). It features on-board USB-Blaster, SDRAM, accelerometer, VGA output, 2x20 GPIO expansion connector, and an Arduino UNO R3 expansion connector in a compact size. The kit provides the perfect system-level prototyping solution for industrial, automotive, consumer, and many other market applications.
The DE10-Lite kit also contains lots of reference designs and software utilities for users to easily develop their applications based on these design resources.
This board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardware is provided on the board:
FPGA Device
- MAX 10 10M50DAF484C7G Device
- Integrated dual ADCs, each ADC supports 1 dedicated analog input and 8 dual function pins
- 50K programmable logic elements
- 1,638 Kbit M9K Memory
- 144 18 × 18 Multiplier
- 4 PLLs
Programming and Configuration
- On-Board USB Blaster (Normal type B USB connector)
Memory Device
- 64MB SDRAM, x16 bits data bus
Sensor
- Accelerometer
Expansion Connectors
- One 2x20 GPIO Connector(voltage levels: 3.3V)
- Arduino Uno R3 Connector, including six ADC channels.
Display
- 4-bit Resistor VGA
Switches/Buttons/LEDs/7-Segment Display
- 10 LEDs
- 10 Slide Switches
- 2 Push Buttons
- Six 7-Segments Display
Power
- 5V DC input
Block Diagram of the DE10-Lite Board
Connectivity
-
Connect with MTL2
-
Connect with D8M-GPIO
- Connect with D5M
- Connect with Arduino Shield
- Connect with LT24
No | 产品名称 | 售价(RMB) |
---|---|---|
1. |
[DE10-Lite] DE10-Lite Board
产品编号: P0466
![]() |
xxx |
2. |
[DE10-Lite] DE10-Lite Board (教育版)
产品编号: P0466
![]() |
xxx |
Documents
标题
版本
档案大小(KB)
新增日期
下载
DE10-Lite User Manual
1.4
6103
2017-01-24

Daughter Card Demonstrations
标题
版本
档案大小(KB)
新增日期
下载
D8M-GPIO
2017-05-18
LT24
2016-09-19
MTL2
2016-09-19
CD-ROM
标题
版本
档案大小(KB)
新增日期
下载
DE10-Lite CD-ROM
2.0.1
2017-08-14
ControlPanel
1.0.2
2017-01-24
Quartus Download
15.1.2
2016-06-21
3D-Printer-Case
标题
版本
档案大小(KB)
新增日期
下载
Top cover
106
2016-08-18

Bottom cover
33
2016-08-18

友晶科技所发表之范例程式码,基於免费分享之原则,不提供任何形式的讲解或修改。如需进一步范例程式码讲解或修改的协助,我们将转至 "设计服务部门" 评估。
本授权条款允许使用者於使用所有友晶及 Altera 开发板时,得以重制、散布、传输以及修改友晶科技提供的源码,但不得为商业目的之使用。使用时必须於引用处表彰友晶科技 (Terasic Inc.) 之商号。
Documents
标题 | 版本 | 档案大小(KB) | 新增日期 | 下载 |
---|---|---|---|---|
DE10-Lite User Manual | 1.4 | 6103 | 2017-01-24 |
![]() |
Daughter Card Demonstrations
标题 | 版本 | 档案大小(KB) | 新增日期 | 下载 |
---|---|---|---|---|
D8M-GPIO | 2017-05-18 | |||
LT24 | 2016-09-19 | |||
MTL2 | 2016-09-19 |
CD-ROM
标题 | 版本 | 档案大小(KB) | 新增日期 | 下载 |
---|---|---|---|---|
DE10-Lite CD-ROM | 2.0.1 | 2017-08-14 | ||
ControlPanel | 1.0.2 | 2017-01-24 | ||
Quartus Download | 15.1.2 | 2016-06-21 |
3D-Printer-Case
标题 | 版本 | 档案大小(KB) | 新增日期 | 下载 |
---|---|---|---|---|
Top cover | 106 | 2016-08-18 |
![]() |
|
Bottom cover | 33 | 2016-08-18 |
![]() |
本授权条款允许使用者於使用所有友晶及 Altera 开发板时,得以重制、散布、传输以及修改友晶科技提供的源码,但不得为商业目的之使用。使用时必须於引用处表彰友晶科技 (Terasic Inc.) 之商号。
Example Designs in System CD
- Factory Default Code
- SDRAM Test in Nios II
- SDRAM Test in Verilog
- VGA Pattern
- Accelerometer Level
- Accelerometer Rock
DE10-Lite Control Panel
Allows users to access various components on the DE10-Lite board from a host computer.
DE10-Lite System Builder
This tool will allow users to create a Quartus II project on their custom design for the DE10-Lite board with the top-level design file, pin assignments, and I/O standard settings automatically generated.
Other course resources you might interested:
School:Cornell UniversitySenior Lecturer - Bruce Land